1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a semiconductor system including a controller and a memory.
2. Related Art
In order to improve the integration degree and capacity of a semiconductor apparatus, or particularly, a memory, a semiconductor system including a plurality of memory chips and a controller to control the plurality of memory chips has been proposed. The controller includes a plurality of memory buffers to communicate with the plurality of memory chips.
FIG. 1 illustrates the configuration of a conventional semiconductor system. The semiconductor system includes a controller 10 and a plurality of memory chips MEMORY0 to MEMORY3 (21 to 24). The controller 10 includes memory buffers RAM0 to RAM4 to communicate with the first to fourth memory chips 21 to 24. The controller 10 basically includes four memory buffers RAM0 to RAM3 corresponding to the number of the first to fourth memory chips 21 to 24 and further include an extra memory buffer RAM4 for dealing with a case in which a data programming fail occurs. The controller 10 including the memory buffers RAM0 to RAM4 performs data communication with the first to fourth memory chips 21 to 24. That is, the memory buffers RAM0 to RAM4 are provided to write data to the first to fourth memory chips 21 to 24 or receive data read from the first to fourth memory chips 21 to 24. Each of the first to fourth memory chips 21 to 24 includes a latch unit LATCH configured to temporarily store data transmitted from the respective memory buffers RAM0 to RAM4 of the controller 10 and a memory cell array configured to store the data stored in the latch unit LATCH.
FIG. 2 illustrates the operation of the semiconductor system of FIG. 1. In particular, FIG. 2 illustrates a data write operation of the semiconductor system. The first to fourth memory buffers RAM0 to RAM3 sequentially transmit data to the first to fourth memory chips MEMORY0 to MEMORY3, and the first to fourth memory chips MEMORY0 to MEMORY3 program the transmitted data into memory cells. The first to fourth memory chips MEMORY0 to MEMORY3 performs the data write operation by performing a data program and verify operation. When all of the first to fourth memory chips MEMORY0 to MEMORY3 successfully perform the data program operation, the fifth memory buffer RAM4 transmits data to the first memory chip MEMORY0, and the first to third memory buffers RAM0 to RAM2 transmit data to the second to fourth memory chips MEMORY1 to MEMORY3, respectively. The first to fifth memory buffers RAM0 to RAM4 maintain the data until they check whether the data transmitted to the first to fourth memory chips MEMORY0 to MEMORY3 were successfully programmed. Therefore, when the programming has succeeded, each of the memory buffers RAM0 to RAM5 erases the data stored therein, receives and stores new data, and prepares the next data write operation.
Referring to FIG. 3, the semiconductor system includes a larger number of memory buffers than the number of the memory chips in order to deal with a case in which a programming fail occurs. When a programming fail occurs, data in which a fail occurs should be reprogrammed into a corresponding memory chip. In FIG. 3, when a programming fail occurs in the first memory chip MEMORY0, the first memory buffer RAM0 does not erase the data that failed to program correctly, but maintains the data. Furthermore, the first memory buffer RAM0 is not updated to store new data. The maintained data is retransmitted to the first memory chip MEMORY0 from the first memory buffer RAM0 during the next data program operation, and the first memory chip MEMORY0 reprograms the data. Therefore, the fifth memory buffer RAM4 transmits new data to the second memory chip MEMORY1, and the second memory chip MEMORY1 programs the data transmitted from the fifth memory buffer RAM4 into a memory cell.
Conventional semiconductor systems include more memory buffers than the number of the memory chips. This configuration causes an area increase of the controller, and reduces the efficiency of the program operation.